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Disambiguation of "De, Vivek"

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Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.

, , , , , , and . ESSCIRC, page 1-4. IEEE, (2019)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Bose

Vivek Shetty

 

Other publications of authors with the same name

A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator., , , , , and . ISSCC, page 404-406. IEEE, (2019)Near-threshold voltage design in nanoscale CMOS.. DATE, page 612. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Monolithic voltage conversion in low-voltage CMOS technologies., , , and . Microelectron. J., 36 (9): 863-867 (2005)Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor., , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 514-522 (2003)Intrinsic MOSFET parameter fluctuations due to random dopant placement., , and . IEEE Trans. Very Large Scale Integr. Syst., 5 (4): 369-376 (1997)Energy-Efficient Computing in Nanoscale CMOS.. IEEE Des. Test, 33 (2): 68-75 (2016)Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 843-856 (2021)On-Die Supply-Resonance Suppression Using Band-Limited Active Damping., , , , , , , , , and 1 other author(s). ISSCC, page 286-603. IEEE, (2007)Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits., and . IEEE J. Solid State Circuits, 48 (4): 895-896 (2013)