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Practical Attacks on Masked Hardware., , and . CT-RSA, volume 5473 of Lecture Notes in Computer Science, page 211-225. Springer, (2009)An introduction to implementation attacks and countermeasures.. MEMOCODE, page 108-115. IEEE, (2009)Evaluation of the Masked Logic Style MDPL on a Prototype Chip., , , and . CHES, volume 4727 of Lecture Notes in Computer Science, page 81-94. Springer, (2007)Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints., and . CHES, volume 3659 of Lecture Notes in Computer Science, page 172-186. Springer, (2005)Kapazitätsorientierte dynamische Losgrößen- und Ablaufplanung bei Sortenproduktion. Kovaÿéc, Hamburg, (1993)Side channel analysis resistant design flow., , , , , , , and . ISCAS, IEEE, (2006)Algebraic Side-Channel Analysis in the Presence of Errors., , , and . CHES, volume 6225 of Lecture Notes in Computer Science, page 428-442. Springer, (2010)Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box., , , and . J. Signal Process. Syst., 50 (2): 251-261 (2008)Evaluation of a DPA-Resistant Prototype Chip., and . ACSAC, page 43-50. IEEE Computer Society, (2009)Potential and Challenges of Harmonizing 40 Years of AVHRR Data: The TIMELINE Experience., , , , , , , , , and 19 other author(s). Remote. Sens., 13 (18): 3618 (2021)