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A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters.

, , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 258-269 (2015)

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A programmable RFSoC in 16nm FinFET technology for wideband communications., , , , , , , , , and 5 other author(s). A-SSCC, page 1-4. IEEE, (2017)A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters., , , , and . ISCAS, page 1-5. IEEE, (2021)16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz., , , , , , , , , and 3 other author(s). ISSCC, page 280-281. IEEE, (2017)A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC., , , , , , , , , and 3 other author(s). VLSI Circuits, page 219-220. IEEE, (2018)6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters., , , , , , , , , and 5 other author(s). ISSCC, page 120-121. IEEE, (2014)An All-Programmable 16-nm RFSoC for Digital-RF Communications., , and . IEEE Micro, 38 (2): 61-71 (2018)A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET., , , , , , , , , and 10 other author(s). VLSI Circuits, page 99-100. IEEE, (2018)Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters., , , , and . IEEE Open J. Circuits Syst., (2021)A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC., , , , and . ICECS, page 1-4. IEEE, (2020)16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC., , , , , , , , , and 3 other author(s). ISSCC, page 276-277. IEEE, (2017)