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A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard.

, , , and . ISCAS (1), page 472-475. IEEE, (2005)

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A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000., , , and . Integr., 39 (1): 1-11 (2005)Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture., , and . J. Supercomput., 40 (2): 127-157 (2007)An early memory hierarchy evaluation simulator for multimedia applications., , and . Microprocess. Microsystems, 38 (1): 31-41 (2014)A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures., , and . IPDPS, IEEE Computer Society, (2005)Early Evaluation of Implementation Alternatives of Composite Data Structures Toward Maintainability., , and . ACM Trans. Softw. Eng. Methodol., 26 (2): 8:1-8:44 (2017)Resource constrained modulo scheduling for coarse-grained reconfigurable arrays., , and . ISCAS, IEEE, (2006)Mapping DSP applications on processor/coarse-grain reconfigurable array architectures., , and . ISCAS, IEEE, (2006)Compiler-Directed Data Locality Optimization in MATLAB., , , and . SCOPES, page 6-9. ACM, (2016)Partitioning Methodology for Heterogeneous Reconfigurable Functional Units., , and . J. Supercomput., 38 (1): 17-34 (2006)MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations., , and . DASIP, page 385-386. IEEE, (2012)