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Disambiguation of "Lin, Jin-Yi"

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A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (12): 2149-2157 (2016)

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Yi Jin

Yi Lin

Hsin-yi Lin

Yi-Ren Lin

Yi-jin Pei

 

Other publications of authors with the same name

A passband lock loop circuit system for band pass filter., and . ISOCC, page 111-112. IEEE, (2016)Temperature-Prediction Based Rate-Adjusted Time and Space Mapping Algorithm for 3D CNN Accelerator Systems., and . IEEE Trans. Computers, 72 (10): 2767-2780 (October 2023)A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS., and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (3): 562-572 (2017)A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (12): 2149-2157 (2016)A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS., and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 70-79 (2015)Thermal-aware architecture and mapping for multi-channel three-dimensional DRAM systems., and . GCCE, page 713-714. IEEE, (2014)Robot Pose and Velocity Estimation Using a Binocular Vision., , , and . FIRA, volume 212 of Communications in Computer and Information Science, page 140-146. Springer, (2011)A low-area digitalized channel selection filter for DSRC system., , and . VLSI-DAT, page 1-4. IEEE, (2014)An 8-bit column-shared SAR ADC for CMOS image sensor applications., , , , , , , , and . ISCAS, page 301-304. IEEE, (2015)A reconfigurable near-data systolic array accelerator for the three-dimensional DRAM systems., , and . GCCE, page 1-2. IEEE, (2016)