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SEALing Neural Network Models in Secure Deep Learning Accelerators.

P. Zuo, Y. Hua, L. Liang, X. Xie, X. Hu, and Y. Xie. CoRR, (2020)

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Jian Xie

Yangpei Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Other publications of authors with the same name

Exploiting Sparsity to Accelerate Fully Connected Layers of CNN-Based Applications on Mobile SoCs.X. Xie, D. Du, Q. Li, Y. Liang, W. Tang, Z. Ong, M. Lu, H. Huynh, and R. Goh. ACM Trans. Embed. Comput. Syst., 17 (2): 37:1-37:25 (2018)NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.X. Xie, X. Hu, P. Gu, S. Li, Y. Ji, and Y. Xie. ACM Trans. Archit. Code Optim., 17 (4): 31:1-31:25 (2020)iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.P. Gu, X. Xie, Y. Ding, G. Chen, W. Zhang, D. Niu, and Y. Xie. ISCA, page 804-817. IEEE, (2020)Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads.A. Basak, S. Li, X. Hu, S. Oh, X. Xie, L. Zhao, X. Jiang, and Y. Xie. HPCA, page 373-386. IEEE, (2019)A Transferable Approach for Partitioning Machine Learning Models on Multi-Chip-Modules.X. Xie, P. Prabhu, U. Beaugnon, P. Phothilimthana, S. Roy, A. Mirhoseini, E. Brevdo, J. Laudon, and Y. Zhou. CoRR, (2021)MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing.X. Xie, P. Gu, Y. Ding, D. Niu, H. Zheng, and Y. Xie. CoRR, (2021)Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training.X. Chen, Y. Wang, X. Xie, X. Hu, A. Basak, L. Liang, M. Yan, L. Deng, Y. Ding, Z. Du and 1 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (4): 936-949 (2022)SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator.X. Xie, Z. Liang, P. Gu, A. Basak, L. Deng, L. Liang, X. Hu, and Y. Xie. HPCA, page 570-583. IEEE, (2021)NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.X. Xie, X. Hu, P. Gu, S. Li, Y. Ji, and Y. Xie. EMC2@HPCA/CVPR/ISCA, page 11-15. IEEE, (2019)SEALing Neural Network Models in Encrypted Deep Learning Accelerators.P. Zuo, Y. Hua, L. Liang, X. Xie, X. Hu, and Y. Xie. DAC, page 1255-1260. IEEE, (2021)

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Disambiguation of "Xie, Xinfeng"

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SEALing Neural Network Models in Secure Deep Learning Accelerators.

Please choose a person to relate this publication to

Jian Xie

Yangpei Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xie, Xinfeng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML SEALing Neural Network Models in Secure Deep Learning Accelerators.

Please choose a person to relate this publication to

Jian Xie

Yangpei Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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SEALing Neural Network Models in Secure Deep Learning Accelerators.