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Disambiguation of "Téllez, Gustavo E."

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Latch Clustering for Timing-Power Co-Optimization.

, , , and . DAC, page 1-6. IEEE, (2020)

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Emilia Téllez

Libia Iris Trejo-Téllez

Victor Téllez Rivera

Claudio Téllez Soto

Carlos Hernando Buitrago-Téllez

 

Other publications of authors with the same name

Clock period constrained minimal buffer insertion in clock trees., and . ICCAD, page 219-223. IEEE Computer Society / ACM, (1994)Design methodology for the IBM POWER7 microprocessor., , , , , , , , , and 15 other author(s). IBM J. Res. Dev., 55 (3): 9 (2011)Minimal buffer insertion in clock trees with skew and slew rate constraints., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (4): 333-342 (1997)On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques., , and . ISPD, page 152-159. ACM, (2018)On Rectilinear Distance-Preserving Trees., and . VLSI Design, 7 (1): 15-30 (1998)On Rectilinear Distance-Preserving Trees., and . ISCAS, page 163-166. IEEE, (1995)Unification of Budgeting and Placement., , and . DAC, page 758-761. ACM Press, (1997)Exploiting Sleep Mode for Memory Partitioning and Other Applications., , and . VLSI Design, 7 (3): 271-287 (1998)Activity-driven clock design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (6): 705-714 (2001)LEO: Line End Optimizer for Sub-7nm Technology Nodes., , and . ISPD, page 117-125. ACM, (2022)