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Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits.

, , , , and . J. Low Power Electron., 7 (3): 364-380 (2011)

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Delay dependent power optimisation of combinational circuits using AND-Inverter graphs., , , and . SoCC, page 9-14. IEEE, (2010)Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators., and . NOCS, page 225-232. ACM/IEEE Computer Society, (2011)HotSpot: Visualizing dynamic power consumption in RTL designs., , , and . EWDTS, page 45-48. IEEE Computer Society, (2008)A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)., , , , , and . Hot Interconnects, page 9-16. IEEE Computer Society, (2012)Network-on-Chip interconnect for pairing-based cryptographic IP cores., , , and . J. Syst. Archit., 57 (1): 95-108 (2011)Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits., , , , and . J. Low Power Electron., 7 (3): 364-380 (2011)A low-power pairing-based cryptographic accelerator for embedded security applications., , , , , and . SoCC, page 369-372. IEEE, (2009)BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation., , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 216-226. Springer, (2009)