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Disambiguation of "Jones, Phillip H."

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The design and integration of a software configurable and parallelized coprocessor architecture for LQR control.

, , , and . J. Parallel Distributed Comput., (2017)

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Phillip H Weidlich

Hugh Jones

Janet Jones-Ullmann

Jens Olaf Jonescheit

Arun W Jones

 

Other publications of authors with the same name

ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation., , and . ASAP, page 185-188. IEEE, (2020)Hardware-software architecture for priority queue management in real-time and embedded systems., , , , , and . Int. J. Embed. Syst., 6 (4): 319-334 (2014)Adaptive Thermoregulation for Applications on Reconfigurable Devices., , , and . FPL, page 246-253. IEEE, (2007)Integrating runtime verification into an automated UAS traffic management system., , , , and . Innov. Syst. Softw. Eng., 18 (4): 567-580 (2022)The design and integration of a software configurable and parallelized coprocessor architecture for LQR control., , , and . J. Parallel Distributed Comput., (2017)An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers., , and . ASAP, page 250-257. IEEE, (2021)Impossible Made Possible: Encoding Intractable Specifications via Implied Domain Constraints., , , , and . FMICS, volume 14290 of Lecture Notes in Computer Science, page 151-169. Springer, (2023)Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads., , and . VLSI Design, page 391-400. IEEE Computer Society, (2007)Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels., , , , , and . ICESS, page 1-8. IEEE, (2019)A project-based embedded systems design course using a reconfigurable SoC platform., , , and . MSE, page 9-12. IEEE Computer Society, (2015)