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Disambiguation of "Gopal, Vinodh"

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Toward Postquantum Security for Embedded Cores.

, , , , , and . IEEE Micro, 39 (4): 17-26 (2019)

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Vinodh Kakkassery

S Vinodh

Karappurath Gopalan

Kreshna Gopal

Gopal Mamdapurkar

 

Other publications of authors with the same name

A hybrid network coding technique for single-hop wireless networks., , , and . IEEE J. Sel. Areas Commun., 27 (5): 685-698 (2009)A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS., , , , , , , , , and . A-SSCC, page 263-266. IEEE, (2018)A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array., , , , , , , , , and 2 other author(s). VLSI Circuits, page 238-. IEEE, (2019)Data De-duplication and Event Processing for Security Applications on an Embedded Processor., , and . SRDS, page 418-423. IEEE Computer Society, (2012)A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS., , , , , , , , , and 2 other author(s). CICC, page 1-4. IEEE, (2019)Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52., , , , and . WAHC@CCS, page 57-62. WAHC@ACM, (2021)Accelerated Processing of Secure Email by Exploiting Built-in Security Features on the Intel EP80579 Integrated Processor with Intel QuickAssist Technology., , and . SRDS Workshops, page 1-8. IEEE Computer Society, (2011)Techniques to Encode and Compress Fault Dictionaries., and . VTS, page 195-200. IEEE Computer Society, (1999)34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms., , , , , , , , , and . ESSCIRC, page 90-93. IEEE, (2018)Toward Postquantum Security for Embedded Cores., , , , , and . IEEE Micro, 39 (4): 17-26 (2019)