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A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner., , and . ESSCIRC, page 87-90. IEEE, (2017)Design of ADPLL system for WiMAX applications in 40-nm CMOS., , , , , and . ICECS, page 73-76. IEEE, (2012)Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications., , and . CICC, page 861-864. IEEE, (2007)All-Digital PLL With Ultra Fast Settling., and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (2): 181-185 (2007)Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS., and . ISCAS, page 1253-1256. IEEE, (2007)Event-driven simulation and modeling of an RF oscillator., , and . ISCAS (4), page 641-644. IEEE, (2004)State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS.. ISCAS, page 229-232. IEEE, (2010)Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator., and . CICC, page 605-608. IEEE, (2005)CMOS RF Circuits for Wireless Applications., , and . EURASIP J. Wireless Comm. and Networking, (2006)Digital RF processing: toward low-cost reconfigurable radios., , and . IEEE Communications Magazine, 43 (8): 105-113 (2005)