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Synthesis of Application Specific Instructions for Embedded DSP Software.

, , , , , and . IEEE Trans. Computers, 48 (6): 603-614 (1999)

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Synthesis of Application Specific Instructions for Embedded DSP Software., , , , , and . IEEE Trans. Computers, 48 (6): 603-614 (1999)Multi-thread VLIW processor architecture for HDTV decoding., , , , , and . CICC, page 559-562. IEEE, (2000)Address code generation for DSP instruction-set architectures., and . ACM Trans. Design Autom. Electr. Syst., 8 (3): 384-395 (2003)A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory., , , , and . IEEE J. Solid State Circuits, 48 (10): 2531-2540 (2013)Virtual Chip: Making Functional Models Work on Real Target Systems., , , , , and . DAC, page 170-173. ACM Press, (1998)Verification of a Microprocessor Using Real World Applications., , , and . DAC, page 181-184. ACM Press, (1999)Improved Sorting Architecture for K-Best MIMO Detection., and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (9): 1042-1046 (2017)Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (5): 2035-2048 (2022)Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset., and . VTC Spring, page 1186-1190. IEEE, (2008)Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000., and . ICIP, page 2665-2668. IEEE, (2009)