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bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.

A. Shokrollahi, D. Carnelli, J. Fox, K. Hofstra, B. Holden, A. Hormati, P. Hunt, M. Johnston, J. Keay, S. Pesenti, R. Simpson, D. Stauffer, A. Stewart, G. Surace, A. Tajalli, O. Amiri, A. Tschank, R. Ulrich, C. Walter, F. Licciardello, Y. Mogentale, and A. Singh. ISSCC, page 182-183. IEEE, (2016)

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Anant Patel

Anant Sahai

Anant Eungwanichayapant

Edwin Ananta

Martin Anantharaman

Other publications of authors with the same name

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.A. Tajalli, M. Parizi, D. Carnelli, C. Cao, J. Fox, K. Gharibdoust, D. Gorret, A. Gupta, C. Hall, A. Hassanin and 20 other author(s). VLSI Circuits, page 92-. IEEE, (2019)A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology.A. Singh, M. Ciraula, D. Weiss, J. Wuu, P. Bauser, P. de Champs, H. Daghighian, D. Fisch, P. Graber, and M. Bron. ISSCC, page 460-461. IEEE, (2009)Physical Insights into Phosphorene Transistor Degradation Under Exposure to Atmospheric Conditions and Electrical Stress.J. Kumar, Ansh, A. Yadav, A. Singh, A. Naclerio, D. Zakharov, P. Kidambi, and M. Shrivastava. IRPS, page 1-4. IEEE, (2020)26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology.A. Singh, D. Carnelli, A. Falay, K. Hofstra, F. Licciardello, K. Salimi, H. Santos, A. Shokrollahi, R. Ulrich, C. Walter and 7 other author(s). ISSCC, page 442-443. IEEE, (2014)Z-RAM® ultra-dense memory for 90nm and below.D. Fisch, A. Singh, and G. Popov. Hot Chips Symposium, page 1-35. IEEE, (2006)10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.A. Shokrollahi, D. Carnelli, J. Fox, K. Hofstra, B. Holden, A. Hormati, P. Hunt, M. Johnston, J. Keay, S. Pesenti and 12 other author(s). ISSCC, page 182-183. IEEE, (2016)Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ.A. Tajalli, M. Parizi, D. Carnelli, C. Cao, K. Gharibdoust, A. Gupta, A. Hassanin, K. Hofstra, B. Holden, A. Hormati and 11 other author(s). CICC, page 1-8. IEEE, (2020)Modelling and Control of Novel Bidirectional Single-Phase Single-Stage Isolated AC-DC Converter with PFC for Charging of Electric Vehicles.A. Singh, R. Prasanna, and K. Rajashekara. EIT, page 661-666. IEEE, (2018)New and "Stronger" Job-Shop Neighbourhoods: A Focus on the Method of Nowicki and Smutnicki (1996).A. Jain, B. Rangaswamy, and S. Meeran. J. Heuristics, 6 (4): 457-480 (2000)Gold Nanoparticle-Based Simple Colorimetric and Ultrasensitive Dynamic Light Scattering Assay for the Selective Detection of Pb(II) from Paints, Plastics, and Water SamplesL. Beqa, A. Singh, S. Khan, D. Senapati, S. Arumugam, and P. Ray. Appl. Mater. Interfaces, 3 (3): 668–673 (2011)

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10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.

Please choose a person to relate this publication to

Anant Patel

Anant Sahai

Anant Eungwanichayapant

Edwin Ananta

Martin Anantharaman

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Singh, Anant"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.

Please choose a person to relate this publication to

Anant Patel

Anant Sahai

Anant Eungwanichayapant

Edwin Ananta

Martin Anantharaman

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.