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Disambiguation of "George, Suma"

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A Programmable and Configurable Mixed-Mode FPAA SoC.

, , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2253-2261 (2016)

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Suma Adindla

Suma Choorapoikayil

Said Mohammad Suma

Hazem Suman

Abdul Hamid Sumadirana

 

Other publications of authors with the same name

Integrated Floating-Gate Programming Environment for System-Level ICs., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2244-2252 (2016)Analog systems education: An integrated toolset and FPAA SoC boards., , and . MSE, page 32-35. IEEE Computer Society, (2015)Neuron Array With Plastic Synapses and Programmable Dendrites., , , and . IEEE Trans. Biomed. Circuits Syst., 7 (5): 631-642 (2013)Modeling and Implementation of Voltage-Mode CMOS Dendrites on a Reconfigurable Analog Platform., , , , and . IEEE Trans. Biomed. Circuits Syst., 6 (1): 76-84 (2012)Truly Heterogeneous HPC: Co-design to Achieve What Science Needs from HPC., , , , , , , , and . SMC, volume 1315 of Communications in Computer and Information Science, page 349-365. Springer, (2020)Shunting Inhibition as a Neural-Inspired Mechanism for Multiplication in Neuromorphic Architectures., and . NICE, page 41-46. ACM, (2023)Performance and Energy Simulation of Spiking Neuromorphic Architectures for Fast Exploration., , , , and . ICONS, page 19:1-19:4. ACM, (2023)Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware., , , , , , and . ISC Workshops, volume 13999 of Lecture Notes in Computer Science, page 538-551. Springer, (2023)Probabilistic Neural Circuits leveraging AI-Enhanced Codesign for Random Number Generation., , , , , , , , , and . ICRC, page 57-65. IEEE, (2022)Neuromorphic Population Evaluation using the Fugu Framework., , , , and . ICONS, page 42:1-42:7. ACM, (2023)