( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A comprehensive variability study of doped HfO2 FeFET for memory applications.

, , , , , , , , и . IMW, стр. 1-4. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Jan van Neerven

Jan van Weeren

Jan van Üüm

Jan ˜vanœ Calker

Jan Van Goethem

 

Другие публикации лиц с тем же именем

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C-V technique., , , , и . Microelectron. Reliab., 47 (4-5): 508-512 (2007)Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness., , , , и . Microelectron. Reliab., 51 (5): 919-924 (2011)A flash memory technology with quasi-virtual ground array for low-cost embedded applications., , , , , , , , , и . IEEE J. Solid State Circuits, 36 (6): 969-978 (2001)Trap-polarization interaction during low-field trap characterization on hafnia-based ferroelectric gatestacks., , , , , , , , , и . IRPS, стр. 12-1. IEEE, (2022)Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors., , , , , , , , , и 1 other автор(ы). IRPS, стр. 10-1. IEEE, (2022)Understanding the memory window in 1T-FeFET memories: a depolarization field perspective., , , , , , , и . IMW, стр. 1-4. IEEE, (2021)Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND., , , , , , , и . IMW, стр. 1-4. IEEE, (2023)Novel level-identifying circuit for flash multilevel memories., , , и . IEEE J. Solid State Circuits, 33 (7): 1090-1095 (1998)Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories., , , , , , , и . Microelectron. Reliab., 52 (3): 525-529 (2012)Transition-state-theory-based interpretation of Landau double well potential for ferroelectrics., , , , , , , , и . CoRR, (2024)