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Disambiguation of "Hanumolu, Pavan Kumar"

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A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC.

, , , , , , , , and . IEEE J. Solid State Circuits, 43 (5): 1195-1206 (2008)

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Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

 

Other publications of authors with the same name

A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS., , , , , , , and . CICC, page 1-4. IEEE, (2020)A Digital PLL With a Stochastic Time-to-Digital Converter., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1612-1621 (2009)Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (11): 2880-2889 (2010)A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (3): 247-251 (2007)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery., , , , , and . IEEE J. Solid State Circuits, 46 (12): 3163-3173 (2011)A 0.016 mm2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS., , and . IEEE J. Solid State Circuits, 54 (8): 2186-2194 (2019)Message From the Incoming Editor-in-Chief.. IEEE J. Solid State Circuits, 54 (8): 2108 (2019)A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC., , , , and . IEEE J. Solid State Circuits, 50 (4): 867-881 (2015)An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW., , and . IEEE J. Solid State Circuits, 48 (2): 487-501 (2013)