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High-Speed Architectures for Multiplication Using Reordered Normal Basis.

, , and . IEEE Trans. Computers, 61 (2): 164-172 (2012)

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A Parallel-In Serial-Out Multiplier Using Redundant Representation for A Class of Finite Fields., , and . ICECS, page 502-505. IEEE, (2006)Improved Area-Time Tradeoffs for Field Multiplication Using Optimal Normal Bases., , , , and . IEEE Trans. Computers, 62 (1): 193-199 (2013)A high speed word level finite field multiplier using reordered normal basis., , and . ISCAS, page 3278-3281. IEEE, (2008)A High-Speed Word Level Finite Field Multiplier in BBF2m Using Redundant Representation., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1546-1550 (2009)An Efficient Finite Field Multiplier Using Redundant Representation., , and . ACM Trans. Embed. Comput. Syst., 11 (2): 31:1-31:14 (2012)Efficient Hardware Implementation of the Hyperbolic Tangent Sigmoid Function., , , , and . ISCAS, page 2117-2120. IEEE, (2009)High speed VLSI implementation of a finite field multiplier using redundant representation., , , , and . ECCTD, page 161-164. IEEE, (2009)High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis., , , , and . IET Circuits Devices Syst., 4 (2): 168-179 (2010)A New Finite-Field Multiplier Using Redundant Representation., , and . IEEE Trans. Computers, 57 (5): 716-720 (2008)A Word-Level Finite Field Multiplier Using Normal Basis., , and . IEEE Trans. Computers, 60 (6): 890-895 (2011)