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Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network., , , and . ISOCC, page 9-10. IEEE, (2017)Power-Efficient Active-RC CT DSM with a Lowpass Capacitor at the Virtual Ground Node of the First Integrator., , and . ISCAS, page 1-4. IEEE, (2018)A charge-pump and comparator based power-efficient pipelined ADC technique., , and . Microelectron. J., 43 (3): 182-188 (2012)A Resistor-Based Sub-1-V CMOS Smart Temperature Sensor for VLSI Thermal Management., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (9): 1651-1660 (2015)An SAR ADC Switching Scheme With MSB Prediction for a Wide Input Range and Reduced Reference Voltage., and . IEEE Trans. Very Large Scale Integr. Syst., 26 (12): 2863-2872 (2018)Quadrature sampling schemes with improved image rejection., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (9): 641-648 (2003)Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (11): 984-988 (2007)A low-latency asynchronous shift register., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 217-221 (2004)A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 1928-1941 (2014)Correction to Ä 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC"., , and . IEEE J. Solid State Circuits, 42 (10): 2315 (2007)