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Exploiting Weak PUFs From Data Converter Nonlinearity - E.g., A Multibit CT ΔΣ Modulator.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (7): 994-1004 (2016)

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Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators., , and . ISCAS (1), page 1037-1040. IEEE, (2003)A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs., , , , and . ISCAS, page 2897-2900. IEEE, (2008)Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators., , and . ISCAS (1), page 1076-1079. IEEE, (2004)Multirate cascaded continuous time Sigma-Delta modulators., , , and . ISCAS (4), page 225-228. IEEE, (2002)A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13μm CMOS with 186MHz GBW., , , , and . ISSCC, page 70-71. IEEE, (2008)A 24-Ch. Multi-Electrode Array Allowing Fast EIS to Determine Transepithelial Electrical Resistance., , , , , , and . BioCAS, page 1-4. IEEE, (2019)Live demonstration: In vivo verification of a 100 Mbps transcutaneous optical telemetric link., , , , and . BioCAS, page 186. IEEE, (2014)Efficient implementation and stability analysis of a HV-CMOS current/voltage mode stimulator., and . BioCAS, page 1-4. IEEE, (2018)Study of Compressed Sensing and Predictor Techniques for the Compression of Neural Signals under the Influence of Noise., and . EMBC, page 1102-1105. IEEE, (2018)A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR., , , , , and . IEEE J. Solid State Circuits, 53 (11): 3256-3267 (2018)