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A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks.

, , , and . ISCAS, page 1520-1523. IEEE, (2014)

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A 12Gbps all digital low power SerDes transceiver for on-chip networking., , , and . ISCAS, page 1419-1422. IEEE, (2011)Optimum positioning of interleaved repeaters in bidirectional buses., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (3): 461-469 (2005)A 16Gbps low power self-timed SerDes transceiver for multi-core communication., , , and . ISCAS, page 1660-1663. IEEE, (2012)The importance of including thermal effects in estimating the effectiveness of power reduction techniques., , and . CICC, page 301-304. IEEE, (2005)PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine., , , and . Integr., (2017)Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting., , , and . MWSCAS, page 1-4. IEEE, (2016)A reference-less multilevel memristor based RRAM module., and . MWSCAS, page 1-4. IEEE, (2015)Physical limitations on the bit-rate of on-chip interconnects., , and . ACM Great Lakes Symposium on VLSI, page 13-19. ACM, (2005)Sperm-shaped magnetic microrobots: Fabrication using electrospinning, modeling, and characterization., , , , , , and . ICRA, page 1939-1944. IEEE, (2016)Real-Time Lane Detection-Based Line Segment Detection., , , , , , , and . NGCAS, page 57-61. IEEE, (2018)