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Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators.

, , , , , and . IEEE Trans. Computers, 64 (8): 2132-2144 (2015)

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Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization., , , , , and . ASAP, page 159-166. IEEE Computer Society, (2010)AxMAP: Making Approximate Adders Aware of Input Patterns., , , and . IEEE Trans. Computers, 69 (6): 868-882 (2020)Designing energy-efficient imprecise adders with multi-bit approximation., , and . Microelectron. J., (2019)Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip., , and . J. Syst. Archit., 59 (7): 516-527 (2013)An adaptive fuzzy logic-based routing algorithm for networks-on-chip., , , , and . AHS, page 208-214. IEEE, (2011)Memristive Data Ranking., , , and . HPCA, page 440-452. IEEE, (2021)Power and delay optimization for network on chip., , and . ECCTD, page 273-276. IEEE, (2005)Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators., , , , , and . IEEE Trans. Computers, 64 (8): 2132-2144 (2015)A tightly-coupled multi-core cluster with shared-memory HW accelerators., , , , , and . ICSAMOS, page 96-103. IEEE, (2012)IDrAx: A tool-chain for designing efficient approximate adders., , , and . Microelectron. J., (2019)