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Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis., , , , and . IOLTS, page 1-8. IEEE, (2022)On error models for RTL security evaluations., , , , , and . DTIS, page 1-6. IEEE, (2014)Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model., , , , , , , , , and 3 other author(s). FDTC, page 1-6. IEEE Computer Society, (2018)Automated Hardware Security Countermeasure Integration Inside High Level Synthesis., , , and . DATE, page 1-2. IEEE, (2024)On a Security-oriented Design Framework for Medical IoT Devices: The Hardware Security Perspective., , , , , and . DSD, page 301-308. IEEE, (2020)Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators., , and . ETS, page 1-2. IEEE, (2021)Laser-Induced Fault Effects in Security-Dedicated Circuits., , , , , , , , , and 5 other author(s). VLSI-SoC (Selected Papers), volume 464 of IFIP Advances in Information and Communication Technology, page 220-240. Springer, (2014)Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor., , , , and . Microprocess. Microsystems, (2019)On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure., , , , and . DATE, page 614-617. IEEE, (2020)You can detect but you cannot hide: Fault Assisted Side Channel Analysis on Protected Software-based Block Ciphers., , , , and . DFT, page 1-6. IEEE, (2020)