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ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs.

, , , , , , and . DAC, page 1-6. IEEE, (2023)

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802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec., , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 65-74. Springer, (2008)Modular Deductive Verification of Multiprocessor Hardware Designs., , , and . CAV (2), volume 9207 of Lecture Notes in Computer Science, page 109-127. Springer, (2015)ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs., , , , , , and . DAC, page 1-6. IEEE, (2023)Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch., and . FCCM, page 145-148. IEEE Computer Society, (2013)High-level synthesis: an essential ingredient for designing complex ASICs., , , and . ICCAD, page 775-782. IEEE Computer Society / ACM, (2004)Getting Formal Verification into Design Flow., , and . FM, volume 5014 of Lecture Notes in Computer Science, page 12-32. Springer, (2008)Designing a reorder buffer in Bluespec.. MEMOCODE, page 93-102. IEEE Computer Society, (2004)Automatic synthesis of cache-coherence protocol processors using Bluespec., , and . MEMOCODE, page 25-34. IEEE Computer Society, (2005)From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols., , , , , and . MEMOCODE, page 71-80. IEEE Computer Society, (2007)H.264 Decoder: A Case Study in Multiple Design Points., , , , , and . MEMOCODE, page 165-174. IEEE Computer Society, (2008)