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Efficient AI System Design With Cross-Layer Approximate Computing.

S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky, N. Cao, T. Fox, B. Fleischer, G. Gristede, M. Guillorn, H. Haynie, H. Inoue, K. Ishizaki, M. Klaiber, S. Lo, G. Maier, S. Mueller, M. Scheuermann, E. Ogawa, M. Schaal, M. Serrano, J. Silberman, C. Vezyrtzis, W. Wang, F. Yee, J. Zhang, M. Ziegler, C. Zhou, M. Ohara, P. Lu, B. Curran, S. Shukla, V. Srinivasan, L. Chang, and K. Gopalakrishnan. Proc. IEEE, 108 (12): 2232-2250 (2020)

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Zhou Zhou

Wilhelm Ching

Paisal Chingduang

Zhou Zhou

Ching-Ching Pan

Other publications of authors with the same name

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.A. Agrawal, S. Lee, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)64-bit prefix adders: Power-efficient topologies and design solutions.C. Zhou, B. Fleischer, M. Gschwind, and R. Puri. CICC, page 179-182. IEEE, (2009)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran and 44 other author(s). ISCA, page 153-166. IEEE, (2021)Synthesis design strategies for energy-efficient microprocessors.C. Zhou, Y. Lin, P. Lu, B. Fleischer, D. Frank, and L. Chang. ICCD, page 103-108. IEEE Computer Society, (2016)14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.M. Kar, J. Silberman, S. Venkataramani, V. Srinivasan, B. Fleischer, J. Rubin, J. Lancaster, S. Lee, M. Cohen, M. Ziegler and 36 other author(s). ISSCC, page 254-256. IEEE, (2024)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)

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Disambiguation of "Zhou, Ching"

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Efficient AI System Design With Cross-Layer Approximate Computing.

Please choose a person to relate this publication to

Zhou Zhou

Wilhelm Ching

Paisal Chingduang

Zhou Zhou

Ching-Ching Pan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhou, Ching"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Efficient AI System Design With Cross-Layer Approximate Computing.

Please choose a person to relate this publication to

Zhou Zhou

Wilhelm Ching

Paisal Chingduang

Zhou Zhou

Ching-Ching Pan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Efficient AI System Design With Cross-Layer Approximate Computing.