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Disambiguation of "Reddy, Sudhakar M."

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On Path Selection in Combinational Logic Circuits.

, , and . DAC, page 142-147. ACM, (1988)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

Other publications of authors with the same name

On Methods to Improve Location Based Logic Diagnosis., , , and . VLSI Design, page 181-187. IEEE Computer Society, (2006)On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression., and . VLSI Design, page 741-744. IEEE Computer Society, (2004)Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality., and . VLSI Design, page 41-46. IEEE Computer Society, (2005)TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits., and . Asian Test Symposium, page 74-. IEEE Computer Society, (1997)Static Test Compaction for Scan-Based Designs to Reduce Test Application Time., and . Asian Test Symposium, page 198-203. IEEE Computer Society, (1998)A method to enhance the fault coverage obtained by output response comparison of identical circuits., and . ITC, page 196-203. IEEE Computer Society, (2001)On RTL scan design., , , , , , and . ITC, page 728-737. IEEE Computer Society, (2001)Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm., , , , , , , and . ITC, page 74-82. IEEE Computer Society, (2002)Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault., , , , and . ITC, page 319-328. IEEE Computer Society, (2003)Minimal Delay Test Sets for Unate Gate Networks., , and . Asian Test Symposium, page 155-. IEEE Computer Society, (1996)