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F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.

Y. Tsubouchi, D. Miyashita, T. Toi, Y. Satoh, F. Tachibana, J. Wadatsumi, M. Morimoto, R. Fujimoto, and J. Deguchi. IEEE J. Solid State Circuits, 54 (4): 1086-1095 (2019)

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Masahisa Deguchi

Jun Jun Lu

Jun Yang

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Jun Yang

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Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.D. Miyashita, S. Kousai, T. Suzuki, and J. Deguchi. A-SSCC, page 25-28. IEEE, (2016)Development of a High Speed Vision System for Mobile Robots.A. Konno, R. Uchikura, T. Ishihara, T. Tsujita, T. Sugimura, J. Deguchi, M. Koyanagi, and M. Uchiyama. IROS, page 1372-1377. IEEE, (2006)Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).A. Amirkhany, T. Karnik, S. Das, J. Deguchi, and Y. Taito. IEEE J. Solid State Circuits, 57 (1): 3-5 (2022)A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.T. Toi, J. Wadatsumi, H. Kobayashi, Y. Shimizu, Y. Satoh, M. Morimoto, R. Ito, M. Ashida, Y. Tsubouchi, M. Nozawa and 3 other author(s). IEEE J. Solid State Circuits, 57 (5): 1517-1526 (2022)A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.F. Tachibana, H. Ngo, G. Urakawa, T. Toi, M. Ashida, Y. Tsubouchi, M. Nozawa, J. Wadatsumi, H. Kobayashi, and J. Deguchi. ESSCIRC, page 505-508. IEEE, (2022)F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology.N. Helleputte, A. Raychowdhury, P. Hsieh, J. Deguchi, M. Perenzoni, E. Rodríguez-Villegas, L. Yan, A. Cathelin, K. Bowman, and C. Hoof. ISSCC, page 520-524. IEEE, (2021)A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS.J. Deguchi, D. Miyashita, Y. Ogasawara, G. Takemura, M. Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda and 3 other author(s). ISSCC, page 456-457. IEEE, (2010)FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.A. Maki, D. Miyashita, K. Nakata, F. Tachibana, T. Suzuki, and J. Deguchi. A-SSCC, page 47-50. IEEE, (2018)A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.T. Toi, J. Wadatsumi, H. Kobayashi, Y. Shimizu, Y. Satoh, M. Morimoto, R. Ito, M. Ashida, Y. Tsubouchi, M. Nozawa and 2 other author(s). ISSCC, page 478-480. IEEE, (2019)Session 4 overview: Imagers.H. Wakabayashi, J. Deguchi, and M. Ikeda. ISSCC, page 64-65. IEEE, (2017)

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Disambiguation of "Deguchi, Jun"

Please choose a person to relate this publication to

Masahisa Deguchi

Jun Jun Lu

Jun Yang

Jun Li

Jun Yang

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Disambiguation of "Deguchi, Jun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.

Please choose a person to relate this publication to

Masahisa Deguchi

Jun Jun Lu

Jun Yang

Jun Li

Jun Yang

Other publications of authors with the same name

Disambiguation