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Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink.

, , , , , and . ICDM, page 330-339. IEEE Computer Society, (2011)

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Using static analysis for coverage extraction fromemulation/prototyping platforms., , , , , and . CODES+ISSS, page 207-214. ACM, (2012)Coverage closure in SoC verification: Are we chasing a mirage?. VTS, page 211. IEEE Computer Society, (2011)Automated Generation and Selection of Interpretable Features for Enterprise Security., , , and . IEEE BigData, page 1258-1265. IEEE, (2018)Learning Semantic Representations to Verify Hardware Designs., , , , , , and . NeurIPS, page 23491-23504. (2021)Efficient Microprocessor Verification using Antecedent Conditioned Slicing., , and . VLSI Design, page 43-49. IEEE Computer Society, (2007)Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs., and . QEST, page 143-152. IEEE Computer Society, (2010)Word level feature discovery to enhance quality of assertion mining., , and . ICCAD, page 210-217. ACM, (2012)Automatic generation of assertions from system level design using data mining., , , and . MEMOCODE, page 191-200. IEEE, (2011)Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm., , and . DATE, page 21-26. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Diagnosing root causes of system level performance violations., , , and . ICCAD, page 295-302. IEEE, (2013)