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Intel's Array Building Blocks: A retargetable, dynamic compiler and embedded language.

, , , , , , , , , , , , and . CGO, page 224-235. IEEE Computer Society, (2011)

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Custom Data Layout for Memory Parallelism., , and . CGO, page 291-302. IEEE Computer Society, (2004)Intel's Array Building Blocks: A retargetable, dynamic compiler and embedded language., , , , , , , , , and 3 other author(s). CGO, page 224-235. IEEE Computer Society, (2011)Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system., , , , and . Microprocess. Microsystems, 29 (2-3): 51-62 (2005)A Case for Combining Compile-Time and Run-Time Parallelization., , , and . LCR, volume 1511 of Lecture Notes in Computer Science, page 91-106. Springer, (1998)Combining compile-time and run-time parallelization., , and . Sci. Program., 7 (3-4): 247-260 (1999)Evaluating Automatic Parallelization in SUIF., , and . IEEE Trans. Parallel Distributed Syst., 11 (1): 36-49 (2000)Increasing the Applicability of Scalar Replacement., and . CC, volume 2985 of Lecture Notes in Computer Science, page 185-201. Springer, (2004)Bridging the Gap between Compilation and Synthesis in the DEFACTO System., , , , and . LCPC, volume 2624 of Lecture Notes in Computer Science, page 52-70. Springer, (2001)A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems., , and . PLDI, page 165-176. ACM, (2002)Using estimates from behavioral synthesis tools in compiler-directed design space exploration., , and . DAC, page 514-519. ACM, (2003)