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SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs.

, , , , , и . MICRO, стр. 796-810. IEEE, (2020)

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Christopher J Garthe

J Christopher Edwards

Christopher J Wickham

Christopher J Wild

Christopher J Kampf

 

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Memory-side prefetching for linked data structures for processor-in-memory systems., и . J. Parallel Distributed Comput., 65 (4): 448-463 (2005)VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs., , , , , , , и . HPCA, стр. 259-272. IEEE, (2023)RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors., , , и . Computer, 35 (2): 40-49 (2002)Hybrid transactional memory., , , , и . PPoPP, стр. 209-220. ACM, (2006)Carbon: architectural support for fine-grained parallelism on chip multiprocessors., , и . ISCA, стр. 162-173. ACM, (2007)Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors., , , , , , , , и . ISCA, стр. 220-231. ACM, (2007)Variability in the execution of multimedia applications and implications for architecture., , , , , и . ISCA, стр. 254-265. ACM, (2001)Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation., , , , и . MICRO, стр. 1-14. ACM, (2017)Performance evaluation of Intel® transactional synchronization extensions for high-performance computing., , , и . SC, стр. 19:1-19:11. ACM, (2013)Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory., , и . PACT, стр. 192-204. IEEE, (2019)