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E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning.

, , , , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (5): 45:1-45:19 (2022)

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An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes., , and . ICC, page 1-5. IEEE, (2009)An embedded FPGA accelerator for a stand-alone dual-mode assistive device., , and . BioCAS, page 1-4. IEEE, (2017)2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection., , , , , , and . DATE, page 728-733. IEEE, (2019)Big vs little core for energy-efficient Hadoop computing., , , , and . DATE, page 1480-1485. IEEE, (2017)A many-core platform implemented for multi-channel seizure detection., , and . ISCAS, page 564-567. IEEE, (2012)Architecture and Evaluation of an Asynchronous Array of Simple Processors., , , , , , , , and . J. Signal Process. Syst., 53 (3): 243-259 (2008)Deep Belief Networks used on High Resolution Multichannel Electroencephalography Data for Seizure Detection., , , and . CoRR, (2017)Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (4): 527-531 (2021)A Hardware Accelerator for Language-Guided Reinforcement Learning., , , , , and . IEEE Des. Test, 39 (3): 37-44 (2022)Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (10): 1757-1770 (2021)