Author of the publication

Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs.

, , , , , , , , , , and . IEEE Des. Test, 36 (3): 39-45 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (12): 2855-2860 (2019)ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2533-2545 (2019)Analysis of Functional Oxide based Selectors for Cross-Point Memories., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (12): 2222-2235 (2016)Dual pillar spin-transfer torque MRAMs for low power applications., , , , , and . JETC, 9 (2): 14:1-14:17 (2013)Device/circuit interactions at 22nm technology node., , and . DAC, page 97-102. ACM, (2009)High-performance low-energy STT MRAM based on balanced write scheme., , and . ISLPED, page 9-14. ACM, (2012)Read-enhanced spin memories augmented by phase transition materials (Invited)., and . MWSCAS, page 993-996. IEEE, (2017)Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed., , , , , , , and . ISVLSI, page 296-301. IEEE Computer Society, (2014)Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs., and . IEEE Des. Test, 30 (6): 29-39 (2013)Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support., , , , , , , , and . CoRR, (2019)