Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An object tracking method using particle filter and scale space model., , , , and . ICIP, page 4081-4084. IEEE, (2009)CMOS Charge Pump With No Reversion Loss and Enhanced Drivability., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (6): 1441-1445 (2014)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)Color2Vec: Web-Based Modeling of Word-Color Association with Sociocultural Contexts., , and . ACM Trans. Comput. Hum. Interact., 30 (4): 51:1-51:29 (August 2023)New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer., , , , , , , and . IEICE Trans. Electron., 93-C (5): 709-711 (2010)Inquiry learning behaviors captured through screencasts in problem-based learning., , , , , , , , and . Interact. Learn. Environ., 26 (6): 839-855 (2018)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)CMOS cross-coupled charge pump with improved latch-up immunity., , , , , , and . IEICE Electron. Express, 6 (11): 736-742 (2009)13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process., , , , , , , , , and 27 other author(s). ISSCC, page 234-236. IEEE, (2024)Performance Evaluation of AODV and DYMO Routing Protocols in MANET., , , and . CCNC, page 1-2. IEEE, (2010)