Author of the publication

Expandable MDC-based FFT architecture and its generator for high-performance applications.

, , , and . SoCC, page 188-192. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A structure-oriented power modeling technique for macrocells., , and . IEEE Trans. Very Large Scale Integr. Syst., 7 (3): 380-391 (1999)Verification of Pin-Accurate Port Connections., , , and . IEEE Des. Test Comput., 25 (5): 478-486 (2008)A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation., , and . IEEE Des. Test Comput., 21 (2): 111-120 (2004)Equivalence checking of scheduling with speculative code transformations in high-level synthesis., , , and . ASP-DAC, page 497-502. IEEE, (2011)A Logical Fault Model for Library Coherence Checking., and . J. Inf. Sci. Eng., 14 (3): 567-586 (1998)An Efficient Power Model for IP-Level Complex Designs., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (8): 2073-2080 (2003)Hybrid Wordlength Optimization Methods of Pipelined FFT Processors., , and . IEEE Trans. Computers, 56 (8): 1105-1118 (2007)Two-level logic minimization for low power., and . ACM Trans. Design Autom. Electr. Syst., 4 (1): 52-69 (1999)An efficient design-for-verification technique for HDLs., , and . ASP-DAC, page 103-108. ACM, (2001)Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs., , , and . ASP-DAC, page 338-343. IEEE, (2013)