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Design of an NoC with on-chip photonic interconnects using adaptive CDMA links.

, , , , and . SoCC, page 352-357. IEEE, (2012)

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Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability., , and . J. Electron. Test., 22 (2): 125-142 (2006)A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs., , , and . VLSI-SoC, page 122-127. IEEE, (2015)Fault-tolerant Quantum Implementation of 1-bit and 4-bit Comparator Circuit using Clifford+T-group., , and . ISED, page 1-6. IEEE, (2019)Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices., , , , , and . IET Comput. Digit. Tech., 15 (2): 112-124 (2021)Modeling and Analysis of 3D IC Structures for Heat Mitigation by Thermal Through Silicon Vias., , , and . ICIIS, page 296-299. IEEE, (2020)Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm., , , , , and . ISMVL, page 40-45. IEEE, (2020)Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)., , and . VLSI Design, page 479-484. IEEE Computer Society, (2007)A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips., , and . DDECS, page 122-128. IEEE Computer Society, (2014)A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips., , , and . Asian Test Symposium, page 25-30. IEEE Computer Society, (2012)Optimization of DC-DC Power Converter Design with Second Generation HiSIM_HV Model., , , , , , and . ISDCS, page 1-5. IEEE, (2019)