Author of the publication

A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing.

, , , , and . Hot Chips Symposium, page 1-29. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing., , , , , , and . ISSCC, page 236-238. IEEE, (2021)The Landscape of Matrix Factorization Revisited., , and . CoRR, (2020)An Upper-Bound on the Required Size of a Neural Network Classifier., and . ICASSP, page 2356-2360. IEEE, (2018)Revisiting the Landscape of Matrix Factorization., , and . AISTATS, volume 108 of Proceedings of Machine Learning Research, page 1629-1638. PMLR, (2020)A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing., , , , and . IEEE J. Solid State Circuits, 55 (9): 2609-2621 (2020)Multi-dataset Low-rank Matrix Factorization., and . CISS, page 1-5. IEEE, (2019)Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs., , , and . VLSI Circuits, page 1-2. IEEE, (2021)A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute., , , and . IEEE J. Solid State Circuits, 54 (6): 1789-1799 (2019)Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing., , , , , , and . IEEE J. Solid State Circuits, 57 (1): 198-211 (2022)A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing., , , , and . Hot Chips Symposium, page 1-29. IEEE, (2019)