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Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design.

, , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 41:1-41:25 (2019)

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A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES., , and . IOLTS, page 104-109. IEEE, (2013)An analytical approach for soft error rate estimation in digital circuits., and . ISCAS (3), page 2991-2994. IEEE, (2005)Instruction cache aging mitigation through Instruction Set Encoding., , , and . ISQED, page 325-330. IEEE, (2016)Application-dependent testing of FPGAs for bridging faults.. FPGA, page 248. ACM, (2003)Soft error rate estimation and mitigation for SRAM-based FPGAs., and . FPGA, page 149-160. ACM, (2005)Reliability-aware Register Binding for Control-Flow Intensive Designs., and . DAC, page 75:1-75:6. ACM, (2014)Runtime adjustment of IoT system-on-chips for minimum energy operation., and . DAC, page 145:1-145:6. ACM, (2018)A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1496-1504 (2020)Reverse Engineering of Printed Electronics Circuits: From Imaging to Netlist Extraction., , , , and . IEEE Trans. Inf. Forensics Secur., (2020)Aging-Aware Design of Microprocessor Instruction Pipelines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (5): 704-716 (2014)