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An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study.

E. Rapuano, G. Meoni, T. Pacini, G. Dinelli, G. Furano, G. Giuffrida, and L. Fanucci. Remote. Sens., 13 (8): 1518 (2021)

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MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs.G. Dinelli, G. Meoni, E. Rapuano, T. Pacini, and L. Fanucci. IEEE J. Emerg. Sel. Topics Circuits Syst., 10 (3): 335-347 (2020)An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick.G. Dinelli, G. Meoni, E. Rapuano, G. Benelli, and L. Fanucci. Int. J. Reconfigurable Comput., (2019)Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator.G. Dinelli, G. Meoni, E. Rapuano, and L. Fanucci. ISCAS, page 1-5. IEEE, (2020)A Complete EGSE Solution for the SpaceWire and SpaceFibre Protocol Based on the PXI Industry Standard.L. Sterpaio, A. Marino, P. Nannipieri, G. Dinelli, D. Davalle, and L. Fanucci. Sensors, 19 (22): 5013 (2019)An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study.E. Rapuano, G. Meoni, T. Pacini, G. Dinelli, G. Furano, G. Giuffrida, and L. Fanucci. Remote. Sens., 13 (8): 1518 (2021)A SpaceFibre multi lane codec System on a Chip: enabling technology for low cost satellite EGSE.P. Nannipieri, G. Dinelli, D. Davalle, and L. Fanucci. PRIME, page 173-176. IEEE, (2018)Design of a SpaceFibre High-Speed Satellite Interface ASIC.P. Nannipieri, G. Dinelli, L. Sterpaio, A. Marino, and L. Fanucci. ApplePies, volume 627 of Lecture Notes in Electrical Engineering, page 483-488. Springer, (2019)A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case.P. Nannipieri, G. Dinelli, and L. Fanucci. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 102-A (5): 747-749 (2019)Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus.G. Dinelli, G. Meoni, P. Nannipieri, L. Sterpaio, A. Marino, and L. Fanucci. ApplePies, volume 627 of Lecture Notes in Electrical Engineering, page 499-504. Springer, (2019)AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA.L. Sterpaio, A. Marino, P. Nannipieri, G. Dinelli, and L. Fanucci. ApplePies, volume 627 of Lecture Notes in Electrical Engineering, page 541-548. Springer, (2019)

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An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study.

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Disambiguation of "Dinelli, Gianmarco"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study.

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