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Disambiguation of "Osana, Yasunori"

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Enhanced Fair Joint Multiple Resource Allocation Method in All-IP Networks.

, and . AINA Workshops, page 163-168. IEEE Computer Society, (2010)

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Other publications of authors with the same name

Programmable Logic Devices (PLDs) in Practical Applications., , and . Principles and Structures of FPGAs, Springer, (2018)Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA., , , , and . IEICE Trans. Inf. Syst., 95-D (10): 2369-2376 (2012)FPL Demo: Kyokko - An Aurora 64b66b compatible 100 Gbps Communication Controller., and . FPL, page 472. IEEE, (2022)An SDR implementation of HF ocean radar on FPGA SoC., and . ICCE, page 1-3. IEEE, (2024)A 100Gbps-ready Low Latency on-Chip Router for FPGA clusters., and . ICCE, page 1-3. IEEE, (2024)A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA., , , , , , , , , and . FPT, page 193-200. IEEE, (2007)Enhanced Fair Joint Multiple Resource Allocation Method in All-IP Networks., and . AINA Workshops, page 163-168. IEEE Computer Society, (2010)A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA., , , , , , , , , and 1 other author(s). ReConFig, page 125-130. IEEE Computer Society, (2009)An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs., , , , and . SIGARCH Comput. Archit. News, 39 (4): 50-55 (2011)Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh., , , , and . IEICE Trans. Inf. Syst., 97-D (5): 1225-1234 (2014)