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Disambiguation of "Balsara, Poras T."

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New Concept for Fault Current Limiter With Voltage Restoration Capability.

, , , , , and . IEEE Trans. Ind. Electron., 67 (12): 10001-10010 (2020)

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Nisha Balsara

T Peters

T Frieberg

T Hohlfeld

T Masselink

 

Other publications of authors with the same name

Multi-clock domain analysis and modeling of all-digital frequency synthesizers., and . ISCAS, page 153-156. IEEE, (2011)Generic Network Interfaces for Plug and Play NoC Based Architecture., , , , , and . ARC, volume 3985 of Lecture Notes in Computer Science, page 287-298. Springer, (2006)Systolic & semi-systolic digit serial multipliers., and . IEEE Symposium on Computer Arithmetic, page 169-173. IEEE Computer Society, (1987)Estimation of passive mixer output bandwidth using switched-capacitor techniques., , , and . CICC, page 1-4. IEEE, (2013)Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications., , and . CICC, page 861-864. IEEE, (2007)New Concept for Fault Current Limiter With Voltage Restoration Capability., , , , , and . IEEE Trans. Ind. Electron., 67 (12): 10001-10010 (2020)Hierarchy embedded differential image for progressive transmission using lossless compression., , , and . IEEE Trans. Circuits Syst. Video Techn., 5 (1): 1-13 (1995)Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (2): 347-359 (2017)All-Digital PLL With Ultra Fast Settling., and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (2): 181-185 (2007)Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (5): 550-554 (2017)