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Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (3): 469-482 (2011)

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Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)Pass-XNOR logic: A new logic style for P-N junction based graphene circuits., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Energy-Efficient Shared Memory Architectures for Multi-Processor Systems-On-Chip., , and . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)Workload-driven frequency-aware battery sizing., , and . ISLPED, page 1-6. IEEE, (2017)Post-placement temperature reduction techniques., , , , and . DATE, page 634-637. IEEE Computer Society, (2010)A State Space Decomposition Algorithm for Approximate FSM Traversal., , , , and . EDAC-ETC-EUROASIC, page 137-141. IEEE Computer Society, (1994)Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (8): 1705-1715 (2014)Composable Battery Model Templates Based on Manufacturers' Data., , , and . IEEE Des. Test, 35 (3): 66-72 (2018)A hierarchical multi-level test generation system., and . Great Lakes Symposium on VLSI, page 54-59. IEEE, (1991)Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting., , , , , and . IEEE Trans. Computers, 48 (8): 769-779 (1999)