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Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems.

, , and . ICCD, page 17-25. IEEE Computer Society, (2018)

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MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation., and . ISCA, page 201-213. ACM, (2017)Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification., , , , , , and . DAC, page 24:1-24:6. ACM, (2016)AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs., , , , and . ASP-DAC, page 45-50. IEEE, (2017)Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems., , and . ICCD, page 17-25. IEEE Computer Society, (2018)Brisk and limited-impact NoC routing reconfiguration., , and . DATE, page 1-6. European Design and Automation Association, (2014)NoCVision: A Network-on-Chip Dynamic Visualization Solution., , , and . NoCArc@MICRO, page 21-26. ACM, (2015)Highly Fault-tolerant NoC Routing with Application-aware Congestion Management., , and . NOCS, page 10:1-10:8. ACM, (2015)Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms., , , , , , , and . ICCAD, page 311-317. IEEE, (2013)Self-Rectifying Characteristics Observed in O-Doped ZrN Resistive Switching Memory Devices Using Schottky Barrier Type Bottom Electrode., , , and . IEEE Access, (2021)Decompose and Conquer: Addressing Evasive Errors in Systems on Chip.. University of Michigan, USA, (2018)