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A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization., , , , , и . IEEE J. Solid State Circuits, 51 (3): 671-685 (2016)A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage., , , , и . IEEE J. Solid State Circuits, 52 (3): 657-668 (2017)A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications., , , , и . IEEE J. Solid State Circuits, 49 (11): 2560-2574 (2014)Power Efficiency Comparisons of Interchip Optical Interconnect Architectures., и . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (5): 343-347 (2010)A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS., , , , , , , , , и . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects., , и . IEEE J. Solid State Circuits, 43 (5): 1235-1246 (2008)Optical I/O technology for tera-scale computing., , , , , , , и . ISSCC, стр. 468-469. IEEE, (2009)3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS., , , , , и . ISSCC, стр. 1-3. IEEE, (2015)A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter., , и . Microelectron. J., 43 (10): 687-696 (2012)A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 1940-1949 (2015)