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Disambiguation of "Chandramouli, Soumya"

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A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)

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Badrish Chandramouli

Soumya Senapati

Krishna Chandramouli

Soumya Sarkar

Chandramouli Chillakuri

 

Other publications of authors with the same name

Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology., , , , and . ISCAS, page 197-200. IEEE, (2007)Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 39 (10): 1659-1670 (2004)A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)A 0.18µm-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels., , , , , , and . ISCAS (5), page 4847-4850. IEEE, (2005)A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication., , , , , , and . ISCAS, page 193-196. IEEE, (2007)A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling., , , , , , and . IWSOC, page 101-106. IEEE Computer Society, (2005)A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS., , , , , , , , , and . CICC, page 1-4. IEEE, (2018)A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS., , , , and . ESSCIRC, page 512-515. IEEE, (2007)