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Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout.

, , and . DAC, page 51:1-51:6. ACM, (2014)

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Double patterning-aware detailed routing with mask usage balancing., , and . ISQED, page 219-223. IEEE, (2014)Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead.. ISPD, page 100-105. ACM, (2001)Voltage Island Generation under Performance Requirement for SoC Designs., and . ASP-DAC, page 798-803. IEEE Computer Society, (2007)Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract)., and . FPGA, page 260. ACM, (1998)A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers., and . ASP-DAC, page 777-782. IEEE, (2006)Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (11): 1822-1835 (2015)A fast hypergraph min-cut algorithm for circuit partitioning., and . Integr., 30 (1): 1-11 (2000)A Bounding Box-based Net Partitioning Method for Double-sided Routing., , , and . ACM Great Lakes Symposium on VLSI, page 397-402. ACM, (2024)Monte Carlo bounding techniques for determining solution quality in stochastic programs., , and . Oper. Res. Lett., 24 (1-2): 47-56 (1999)A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules., , and . ASP-DAC, page 501-506. IEEE, (2014)