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Disambiguation of "Ellguth, Georg"

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Dynamic voltage and frequency scaling for neuromorphic many-core systems.

, , , , , , , , , , , , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)

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Peter Ellguth IAB Nürnberg

Martin Ellguth

Jennifer Sara Ellguth

David Georg

Jens Georg

 

Other publications of authors with the same name

Low power design of the X-GOLD® SDR 20 baseband processor., , , , , , , and . DATE, page 792-793. IEEE Computer Society, (2010)Hardware Implementation of an OPC UA Server for Industrial Field Devices., , , , , , , , , and 6 other author(s). CoRR, (2021)Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 10 other author(s). ISCAS, page 1. IEEE, (2017)A low-power cell-based-design multi-port register file in 65nm CMOS technology., , , and . ISCAS, page 313-316. IEEE, (2010)Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS., , , , , , , , and . VLSI-SoC, page 155-158. IEEE, (2019)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing., , , , , , , , , and 8 other author(s). CoRR, (2021)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). CoRR, (2019)A power management architecture for fast per-core DVFS in heterogeneous MPSoCs., , , , , and . ISCAS, page 261-264. IEEE, (2012)A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI., , , , , , , , , and 3 other author(s). IEEE Trans. Biomed. Circuits Syst., 16 (1): 94-107 (2022)