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Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores., , , and . PDPTA, CSREA Press, (2000)Probabilistic Fault Grading for AI Accelerators using Neural Twins., , and . ISVLSI, page 333-338. IEEE, (2022)Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis., , , and . ISVLSI, page 128-133. IEEE, (2022)Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*., , and . ETS, page 1-6. IEEE, (2023)Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing., , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Authentication of sensor network flooding based on neighborhood cooperation., and . WCNC, page 665-670. IEEE, (2006)Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration.. ACM Great Lakes Symposium on VLSI, page 1. ACM, (2015)Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs., , and . DAC, page 685-690. ACM, (2002)Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems., , and . CODES+ISSS, page 377-378. ACM, (2011)Cross-contamination avoidance for droplet routing in digital microfluidic biochips., and . DATE, page 1290-1295. IEEE, (2009)