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24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS., , , , , , , and . ISSCC, page 420-422. IEEE, (2016)Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture., and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 278-292. Springer, (2009)16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS., , , , , and . ISSCC, page 280-281. IEEE, (2014)Fast Simulation Framework for Subthreshold Circuits., , and . ISCAS, page 2549-2552. IEEE, (2009)Design of low-power, scalable-throughput systems at near/sub threshold voltage., , and . ISQED, page 609-616. IEEE, (2012)Analog Matrix Processor for Edge AI Real-Time Video Analytics., , , , and . ISSCC, page 260-262. IEEE, (2022)A case for NEMS-based functional-unit power gating of low-power embedded microprocessors., , and . DAC, page 872-877. ACM, (2011)Design techniques for functional-unit power gating in the Ultra-Low-Voltage region., and . ASP-DAC, page 609-614. IEEE, (2012)Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part I - Analog Circuit Techniques., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2237-2249 (2017)A low-power parallel design of discrete wavelet transform using subthreshold voltage technology., , and . CASES, page 235-244. ACM, (2008)