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NN-Baton: DNN Workload Orchestration and Chiplet Granularity Exploration for Multichip Accelerators., , , and . ISCA, page 1013-1026. IEEE, (2021)YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip., , , , , , , , and . DAC, page 1093-1098. ACM, (2022)PCNN: Pattern-based Fine-Grained Regular Pruning Towards Optimizing CNN Accelerators., , , , , , , , , and 1 other author(s). DAC, page 1-6. IEEE, (2020)Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators., , , , , , , and . HPCA, page 156-171. IEEE, (2024)A Scalable Multi-Chiplet Deep Learning Accelerator with Hub-Side 2.5D Heterogeneous Integration., , , , , and . HCS, page 1-17. IEEE, (2023)Finding the Task-Optimal Low-Bit Sub-Distribution in Deep Neural Networks., , , , and . CoRR, (2021)Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators., , , , , , , and . CoRR, (2023)Cocco: Hardware-Mapping Co-Exploration towards Memory Capacity-Communication Optimization., , and . ASPLOS (1), page 69-84. ACM, (2024)SCAN: A Scalable Neural Networks Framework Towards Compact and Efficient Models., , , , , and . NeurIPS, page 4029-4038. (2019)A 400MHz NPU with 7.8TOPS2/W High-PerformanceGuaranteed Efficiency in 55nm for Multi-Mode Pruning and Diverse Quantization Using Pattern-Kernel Encoding and Reconfigurable MAC Units., , , , , and . CICC, page 1-2. IEEE, (2021)