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Simulation and satisfiability guided counter-example triage for RTL design debugging.

, , , and . ISQED, page 618-624. IEEE, (2014)

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Automated silicon debug data analysis techniques for a hardware data acquisition environment., , , , and . ISQED, page 675-682. IEEE, (2010)Simulation and satisfiability guided counter-example triage for RTL design debugging., , , and . ISQED, page 618-624. IEEE, (2014)Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs., , , and . DATE, page 996-1001. IEEE Computer Society, (2005)Seamless Integration of SER in Rewiring-Based Design Space Exploration., , , and . ITC, page 1-9. IEEE Computer Society, (2006)A failure triage engine based on error trace signature extraction., , and . IOLTS, page 73-78. IEEE, (2013)Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (6): 1118-1131 (2012)Sequential logic rectifications with approximate SPFDs., , , , and . DATE, page 1698-1703. IEEE, (2009)Automating Logic Transformations With Approximate SPFDs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (5): 651-664 (2011)Automating Logic Rectification by Approximate SPFDs., , , and . ASP-DAC, page 402-407. IEEE Computer Society, (2007)Extraction error modeling and automated model debugging in high-performance custom designs., , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (7): 763-776 (2006)