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Disambiguation of "Chung, JaeWoong"

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Architectural Semantics for Practical Transactional Memory.

, , , , , , and . ISCA, page 53-65. IEEE Computer Society, (2006)

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Hae-Bon Chung

Dai-Hai Chung

Chong-Woon Chung

Jae-hee Chung

Chen-Yu Chung

 

Other publications of authors with the same name

Ased: availability, security, and debugging support usingtransactional memory., , , , , and . SPAA, page 366. ACM, (2008)Optimizing the Concurrent Execution of Locks and Transactions., and . LCPC, volume 7146 of Lecture Notes in Computer Science, page 124-140. Springer, (2011)Characterization of TCC on Chip-Multiprocessors., , , , , , , and . IEEE PACT, page 63-74. IEEE Computer Society, (2005)Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU., , , , , , and . DAC, page 888-896. ACM, (2012)Towards soft optimization techniques for parallel cognitive applications., , , , and . SPAA, page 59-60. ACM, (2007)THEMIS: A Mutually Verifiable Billing System for the Cloud Computing Environment., , , and . IEEE Trans. Serv. Comput., 6 (3): 300-313 (2013)Tradeoffs in transactional memory virtualization., , , , , , , and . ASPLOS, page 371-381. ACM, (2006)Architectural Semantics for Practical Transactional Memory., , , , , , and . ISCA, page 53-65. IEEE Computer Society, (2006)Extended Synchronous Dataflow for Efficient DSP System Prototyping., , and . IEEE International Workshop on Rapid System Prototyping, page 196-. IEEE Computer Society, (1999)STAMP: Stanford Transactional Applications for Multi-Processing., , , and . IISWC, page 35-46. IEEE Computer Society, (2008)